Implementation of Soft Error-Resilient Built-In 2d Hamming Product Code Using Verilog | Original Article

ABSTRACT:

Radiation_induced soft error rate (SER) degrades the reliability of static random access memory(SRAM)-based field programmable gate arrays (FPGAs).This paper presents a new built-in 2-D Hamming product code (2-D HPC)scheme to provide reliable operation of SRAM-based FPGAs in hostile operating environments such as space.Multibit error correction capabilit such as space.Multibit error correction capability of our built-in 2-D HPC can improve the reliability ,and hence ,system availability ,by orders of magnitude.Simulation results show that the large number of error correction capability of 2-D HPC can recover configuration bits without depending on an external memory preserving a golden copy of the configuration bits. To provide efficient 2-D HPC in a built-in logic ,we also propose a new 2-D SRAM buffer.Using the proposed multibit error correction scheme,system availability of an SRAM-based FPGA can be more than 99.9999999% with SRAM cell faiure in 1 billion h of operation of 7.