Study on Hierarchy Representation In Neural Network |

ABSTRACT:

Before discussing static-analysis tools, it is useful to examine someoperations that simplify the job. In many IC layout systems, the connectivityis not specified, but must be derived from the geometry. Since connectivity iscrucial to most circuit-analysis tools, it must be obtained during or immediatelyafter design. Ideally, network maintenance should be done during design as newgeometry is placed [Kors and Israel], but the more common design system waitsfor a finished layout. The process of converting such a design from puregeometry to connected circuitry is called node extraction. Node extraction of IC layout can be difficult and slow due to thecomplex and often nonobvious interaction between layers. In printed-circuitboards, there is only one type of wire and its interactions are much simpler.This allows PC node extraction to be easily combined with other analysis toolssuch as design-rule checking [Kaplan]. Integrated-circuit node extraction must recognize layer configurationsfor complex components. In MOS layout, for example, the recognition oftransistors involves detection of the intersection of polysilicon anddiffusion, with or without depletion and tub implants, but without contact cutsand buried implants. Rules for detecting such combinations are specially codedfor each design environment and can be applied in two different ways:polygon-based or raster-based. Polygon-based node extraction uses the complexgeometry that is produced by the designer, whereas raster-based node extractionreduces everything to a fine grid of points that is simpler to analyze.