This Paper Reports Comparator Design For Low Power & High Speed. the Present Design Is Specially Design For High Resolution Sigma Delta Analog to Digital Converters (Sdadcs). Design Is Based on Two Stage Cmos Op-Amp Technique. Simulation Results Have Been Obtained By 0.5 Micron Technology, Considering ±2.5 Supply Voltage & 2.5 V Input Range.Design Has Been Carried Out In Tanner Tool Using Hp 0.5 Micron Technology.Simulation Results Are Verified Using S-Edit and W-Edit. We Have Achieved the Propagation Delay (Speed) of 3.6 Nanosec. With Low Power Consumption About 0.31 Mw. Finally, Compare the Proposed Results With Earlier Work Done [5], [10]And Get Improvement In Presented Results.