Registerfile Access In Risc Processors Is Highly Asymmetric In Nature; a Relativelysmall Number of Registers Account For a Majority of the Register File Accessesduring Program Execution. This Is Mostly Because the Lifetime of Typicalprogram Variables Is Very Small and a Small Number of Registers Are Heavilyreused. Also, Because of Calling Conventions Followed In Most Risc Processors;These Are Rules Enforced By the Software During Procedure Call on We Propose Astrategy to Determine an Application-Specific Register File Banking Structureand an Appropriate Register Mapping Strategy That Minimizes Power Dissipationin the Register File. a Straight Forward Method to Identify the Best Bankstructure Is to Exhaustively Simulate All Possible Configurations of Bankingand Choose the Configuration Yielding Maximum Power Reduction. But Thisapproach Is Infeasible If the Number of Registers Is Large; Moreover, There Arean Exponentially Large Number of Different Mappings of Logical to Physicalregisters (Register Allocation Decisions).